Conventionally, information reproduction apparatuses (e.g., a read channel LSI core) for reproducing data and timing from an analog signal (e.g., an output signal from an optical pickup of a DVD) comprising data information and timing information have been disclosed in Non-Patent Document 1 (Floyd M. Gardner, “Interpolation in Digital Modems—Part I: Fundamentals”, IEEE Transactions on Communications, Vol. 41, No. 3, p. 501-507, March, 1993), and Patent Document 1 (Japanese Published Patent Application No. Hei. 9-204622).
Both the information reproduction apparatuses disclosed in these literatures are constituted such that an analog signal that is read from an information recording medium is digitized with a clock that is not necessarily synchronized with a timing included in the analog signal, and then the timing is recovered by interpolation.
Hereinafter, the process of reproducing data and timing recorded on a medium such as a DVD by the above-mentioned construction will be described with reference to FIG. 13.
FIG. 13 is a diagram for explaining the conventional information reproduction apparatus.
The conventional information reproduction apparatus 1300 reproduces data and timing from an analog signal that is recorded on a medium 1301 such as a DVD and comprises data information and timing information, and the apparatus 1300 includes an ALPF (Analog Low Pass Filter) 1302, an A/D converter (ADC) 1303, a frequency synthesizer 1304, an interpolator 1305, a DEQ (Digital Equalizer) 1306, a TR (Timing Recovery Logic) circuit 1307, a controller 1308, a FIR (Finite Impulse Response) circuit 1309, and a Viterbi decoder 1310.
The ADC 1303 converts the analog signal that is read from the medium 1301 into a digital signal, and outputs the digital signal to the interpolator 1305. The frequency synthesizer 1304 supplies a clock of a predetermined frequency to the ADC 1303, the interpolator 1305, and the controller 1308. The interpolator 1305 generates a clock that is pseudo-synchronized with the timing of data recording into the medium 1301, and supplies the clock to the controller 1308, the FIR 1309, and the Viterbi decoder 1310. The DEQ 1306 equalizes a predetermined frequency component of the output signal from the interpolator 1305. The FIR circuit 1309 equalizes the output of the DEQ 1306 so that the output of the DEQ 1306 becomes a signal suited to a target PR system. The Viterbi decoder 1310 reproduces the data recorded on the medium 1301 on the basis of the output signal from the FIR circuit 1309.
Next, the operation will be described.
The data and timing recorded on the medium 1301 such as a DVD is read by an optical pickup (not shown) and reproduced as an analog signal. The analog data is amplified and offset-controlled so as to be suited to the input range of the ADC 1303 by a variable gain amplifier (VGA) (not shown) and an offset controller (not shown) which are provided in a stage prior to the ALPF 1302, respectively. Thereafter, the analog signal is inputted to the ALPF 1302, and a high frequency component thereof is removed. The analog signal outputted from the ALPF 1302 is converted into a digital signal by the ADC 1303. At this time, a sampling clock is supplied from the frequency synthesizer 1304. This clock is not necessarily synchronized with the timing clock that is recorded on the medium such as a DVD, and generally, it is a clock of a frequency faster than the timing clock. Further, the output clock of the frequency synthesizer 1304 is also inputted to the interpolator 1305 and the controller 1308.
The digital signal outputted from the ADC 1303 is not synchronized with the timing of the data recorded on the medium 1301. The interpolator 1305 synchronizes the digital signal with the timing by interpolation. That is, the interpolator 1305 receives information corresponding to a phase difference between the sampling clock and the timing from the controller 1308, and performs interpolation according to the phase difference to make synchronization. Further, the interpolator 1305 generates a clock that is pseudo-synchronized with the timing by thinning the sampling clocks.
The DEQ 1306 equalizes the output signal of the interpolator 1305. Since a DVD has a tendency that the amplitude of a high frequency component (e.g., 3T+3T pattern) decreases, the DEQ 1306 amplifies such component.
The TR circuit 1307 performs timing recovery using the output of the DEQ 1306. In the case of a DVD, since SYNC marks of 14T+4T appear at intervals of 1488T as shown in FIG. 14, the TR circuit 1307 detects a frequency error by detecting the interval between a SYNC mark and a SYNC mark. Further, the TR circuit 1307 detects a phase error on the basis of the value of a zerocross point. The frequency error and the phase error are inputted to the controller 1308.
The controller 1308 obtains an error between the sampling clock and the recorded timing on the basis of the frequency error and the phase error.
As described above, a timing recovery loop is constituted by the interpolator 1305, the DEQ 1306, the TR circuit 1307, and the controller 1308, and thereby timing recovery is carried out.
On the other hand, the output of the DEQ 1306 is inputted to the FIR circuit 1309. The FIR circuit 1309 further equalizes the output of the DEQ 1306 so that the output of the DEP 1306 becomes a signal suited to the target PR system (e.g., PR(3,4,4,3)).
The Viterbi decoder 1310 performs error correction to the output of the FIR circuit 1309 by maximum likelihood decoding based on the Viterbi algorithm, whereby the data recorded on the medium 1301 is reproduced.
Further, FIG. 15 shows a conventional information reproduction apparatus that is different from the above-described information reproduction apparatus 1300 in the construction of the timing recovery loop. FIG. 15 is a diagram illustrating the second conventional information reproduction apparatus. The information reproduction apparatus 1500 shown in FIG. 15 is difference from the information reproduction apparatus 1300 shown in FIG. 13 in the construction of the timing recovery loop. In the information reproduction apparatus 1500 shown in FIG. 15, the timing recovery loop is constituted by an ADC 1303, a DEQ 1306, a TR circuit 1307, a D/A converter (DAC) 1502, and a VCO (Voltage Controlled Oscillator) 1503.
The DAC 1502 converts the frequency information outputted from the TR circuit 1307 into an analog voltage. The VCO 1503 outputs a clock of a frequency based on the voltage value outputted from the DAC 1502.
Hereinafter, a description will be given of the timing recovery operation in the timing recovery loop constituted as described above.
The output of the ADC 1303 is equalized by the DEQ 1306 and outputted to the TR circuit 1307. The TR circuit 1307 calculates frequency information comprising a frequency error and a phase error on the basis of the output signal of the DEQ 1306. The DAC 1502 converts the frequency information outputted from the TR circuit 1307 into an analog voltage. The VCO 1503 generates a clock of a frequency based on the output voltage of the DAC 1502. The clock outputted from the VCO 1503 is supplied to the ADC 1303, the DAC 1502, the DEQ 1306, and the TR circuit 1307, and the frequency of the clock outputted from the VCO 1503 is synchronized with the data recording timing onto the medium 1301 by the feedback control.